Very Large-Scale Integration (VLSI) Technology Future


 


VLSI is dominated by the CMOS technology and much like other logic families, this too has its limitations which have been battled and improved upon since years. Taking the example of a processor, the process technology has rapidly shrunk from 180 nm in 1999 to 60nm in 2008 and now it stands at 45nm and attempts being made to reduce it further (32nm) while the Die area which had shrunk initially now is increasing owing to the added benefits of greater packing density and a larger feature size which would mean more number of transistors on a chip.

Architecture :


VLSI or UVLSI field will be very exciting near future, as all semiconductor firms are working 

hard to bring AI and Machine Learning chips, to accelerate the computing. Adding to that

 Google is working on TPU (Tensor Processor Units), for future high performance datacenter 

and cloud infrastructure.

Fabrication:

On other side fabrication process is reaching its new horizons to new level each day. TSMC 

already started building 5nm roadmap for next generation chipsets. Also researchers are 

working on manufacturing yield enhancement.



Challenges :

Power power power.

As boom in handheld device market, all of us want to have long battery life. Chip Designers, 

Architects are spending time to enhance battery run time.

I have listed things which I felt current and future industry will look like. Its very exciting to be

 part of this journey.


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